Embodiments of the disclosure disclosed herein relate to a semiconductor device, and more particularly, to a data training method of a storage device for performing data training at high speed.
There is a need for data training (or DQ training) to secure the reliability of data in a storage device implemented with a plurality of nonvolatile memory devices and a storage controller. The data training includes read training and write training. The read training refers to an operation in which the storage controller aligns the center of an eye pattern of data Dout output from a nonvolatile memory device. The write training refers to an operation for aligning an eye pattern of data Din to be written in a nonvolatile memory device.
For the data training, the storage controller may write data of a specific pattern in the nonvolatile memory devices respectively or may read data of a specific pattern from a nonvolatile memory device. A command and an address are necessary to write or read data of a specific pattern. Accordingly, a time taken to input a command and an address and to input or output pattern data and a time for AC timing are inevitably required during a training operation.
To implement a high-capacity storage device, the large number of nonvolatile memory devices may be mounted on the storage device. In the storage device including the large number of nonvolatile memory devices, there is a need to reduce open timing for the purpose of providing speedy access performance in a situation such as power-up.